Introduction

SystemVerilog is a hardware description language (HDL) to model, simulate, and verify electronic systems. It is standardized as IEEE-1800 with latest revision in 2017. This chapter will cover its history, provide some simply example to get started, and conclude with the scope of this book. At the end of this chapter you should understand why SystemVerilog is the de facto standard for modern hardware systems design and verification and how this book can help you learn SystemVerilog.

1.1 A brief history of SystemVerilog

SystemVerilog is the ultimate combination following language designs as well as other technologies donation such as BlueSpec:

1. Verilog, which is an IEEE standard (IEEE 1364);
2. Superlog, donated to Accellebra from the startup company Co-Design Automation (acquired by Synopsys);
3. OpenVera, donated by Synopsys.

Before we delve into the history of SystemVerilog, we need to take a step back and appreciate the evolution of Verilog, SystemVerilog’s precursor. Verilog was original develop between 1983 and 1984 and the company that created the language was eventually bought by Cadence in 1990. About 10 years later, Verilog is transferred by Cadence into the public domain and latter submitted to IEEE and becomes IEEE 1364-1995 standard, commonly referred as Verilog-95.

As Verilog gained much popularity, significantly improvement had been made into Verilog-95, leading to a newer version of the standard, IEEE 1364-2001, known as Verilog-2001. Lots of syntax enhancement made the language simpler and more expressive.

IEEE 1364-2005 is the last version of Verilog, where minor improvements were made into the standard. This standard marks the end of Verilog and was later merged into SystemVerilog and became a subset of SystemVerilog in IEEE 1800-2009.

One common misconception is that Verilog is the HDL that is synthesizable, that is, able to be synthesized by the synthesis tools, and SystemVerilog is a verification language not synthesizable. This is completely wrong as Verilog is a strict subset of SystemVerilog and only a subset of SystemVerilog is synthesizable. The confusion got worse when the IEEE 1364-2005 (Verilog) merged with IEEE 1800-2005 (SystemVerilog) and the name “Verilog” ceased to exist in IEEE’s nomenclature. We will use SystemVerilog throughout the book, but you may hear people use Verilog when referring to SystemVerilog.

With the donation from Superlog, SystemVerilog gains advanced syntax to boost design productivity, such as struct and enum, which itself is heavily influenced by C/C++. OpenVera greatly enhanced SystemVerilog’s ability to express assertion under various conditions, easing simulation coverage collection and formal verification.

Asides from the unification of these three languages, SystemVerilog also introduce the concept of object-oriented-programming (OOP), which is influenced by C++ and Java. Unfortunately, design code that uses OOP cannot be synthesized for all synthesis tools, yet it is still commonly used in verification.

First standardized in 2005 as IEEE 1800-2005, SystemVerilog enjoys a new and refined standard every 4-5 years. IEEE 1800-2009 marked the maturity of SystemVerilog as it merges in Verilog and integrates with Verilog-AMS. It also ensures interoperability with other HDLs such as SystemC and VHDL. Two subsequent revision standard IEEE 1800-2012 and IEEE 1800-2017 further refined and clarified the language specification.

In introspect, the entire digital system design community witnessed the trend where a number of proprietary design languages fight for market and the only winners are the one that open up their specification. Remaining open allows EDA vendors as well as designers voice their critiques and concerns during the standardization process, which lead to wider adoption. There was a significant amount of concern in early 2010s where designers were uncertain whether SystemVerilog would ever be used. However, almost a decade later SystemVerilog is used by most hardware companies and supported by all popular EDA vendors.

1.2 Getting started

SystemVerilog files are text-based and end mostly in .sv for implementation and .svh for header and definition files. Some EDA tools, e.g. Verilator, can parse SystemVerilog from normal Verilog file extension (.v), but most tools will report syntax error and a special flag needed to inform their internal language parser. In this book we will use .sv and .svh for file extensions.

We will use the simple hello world example to help you get started. Save the following code as example1.sv.

module example1;

initial begin
    $display("hello world");
end

endmodule

To run it, simply do

$ xrun example1.sv

You will see the following output along with other compilation information in the console output.

xcelium> run
hello world

1.2.1 A note on EDA tools used in the book

By default, the book assumes you have the following commercial EDA tools installed:

1. Xcelium, which provides xrun command.
2. JasperGold, which provides jaspergold command.

While we understand that accessing these tools is difficult for most people, given their absurd license cost, these tools are selected due to their support for SystemVerilog features covered in this book. If you only have access to VCS, you should be able to run all the code examples by translating the simulator flags appropriately.

If you do not have access to any commercial EDA tools, you can use EDA Playground for free. Notice that you have to register an account and accept its limited use terms. Most of the design and simulation code used here can be run on EDA Playground. Unfortunately EDA Playground does not have JasperGold installed.

That being said, if you really need to use FOSS software, here is a list of tools that might work with the code examples below. However, we will not cover any command in this book, nor will we offer workaround to run the tools in case things do work.

1. iverilog
2. Verilator
3. yosys. Notice that you need to purchase a Verific licence so that yosys can parse SystemVerilog files. The default support for SystemVerilog in yosys is very limited.

1.3 A gentle introduction on digital systems

Digital system has been studied for decades and its complexity warrants several books to cover the content in details. This chapter will only cover the basics and we will introduce more digital system concepts as we learn more SystemVerilog.

1.3.1 Number systems

There are many ways to represent numbers in digital systems. The most approach is called positional number representation: a number \(N\) with \(n\) digits can be represented as followings with base \(b\): \[ (N)_{b} = d_{n-1} \times b^{n-1} + d_{n-2} \times b^{n-2} + \dots + d_0 \times b^0 \]

Due to the usage of logic gates, where data is represented as 0’s and 1’s, base 2, 8, 10, and 16 are commonly used in practice. Depends on the design needs, people choose one base over another for a particular number. For instance, if a number is used for storing flag information, then binary representation would be a better idea; if the number is used for instructions, then hexadecimal representation could be easier to read. Nevertheless, keep in mind that these are just different representation for the same number: choosing different base does not change the actual value of the number.

Unlike natural numbers where there is no upper bound of maximum value, numbers in digital systems have a maximum value determined by its bit width. For instance, for a 4-bit number, the maximum value is \(2^4 - 1 = 15\). One direct implication for that is overflow, where the arithmetic operation result is bigger than the maximum value defined by the bit width. Overflow occurs very often and should be treated with extreme care.

Another important attribute about number systems is that the number can be either signed or unsigned. Although the value of each bit remains the same, signed or unsigned representation can change the values of the number. For an unsigned number, the actual value and arithmetics follows that of natural numbers. For a signed number, the most common approach is using two’s complement. For instance, suppose we have a 4-bit number and we want to represent \(-2\). The procedure is as follows:

1. represent \(|-2| = 2\) in binary, which is \(0010\);
2. invert each bit, which is \(1101\);
3. add 1 to the previous result, which becomes \(1110\).

After the procedure, \(-2\) can be represented as \(1110\) using two’s complement. To simply check if the arithmetic works out under two’s complement scheme, we can compute \((-2) + 4\) as follows: \[ (-2)_{10} + 4_{10} = 1110_{2} + 0100_{2} = 0010_{2} = 2_{10} \] Notice that although the addition overflows, it is intentional. Using two’s complement, we can reuse all the arithmetics and let arithmetic overflowing taking care of the sign, which is the major advantage of using two’s complement.

1.3.2 Boolean algebra and logic gates

Boolean algebra is the branch of algebra where the values of the variable are either true or false. It was introduced by George Boole in 1847, hence the name boolean. Boolean algebra is fundamental in the development of digital systems. It is particularly used in logic synthesis, where the synthesis tools use boolean algebra to simplify the circuit while maintaining the same logic. Commonly used boolean algebra theory include Consensus Theorem and DeMorgan’s Theorem. Due to the scope of the book, we will not cover boolean algebra in details.

Logic gates are the building blocks of a digital system. Commonly used logic gates such as AND, OR, XOR, and NOT gate. These gates can be wired tother to form more useful logic blocks such as multiplexer and adder.

In many cases, a logic gate is abstracted as a block that dissipates no power and changes its value instantaneously whenever the inputs changes, a.k.a. ideal logic gate. Its behavior can be described mathematically as a step function, a visualization commonly shown in the debug interface. In reality, however, the logic gates does dissipates power, and it cannot change its output instantaneously, a delay called propagation delay that is critical to the timing analysis.

In addition, contrary to ideal logic gate where the value can either be 0 or 1, real logic gate can exhibit un unstable equilibrium or metastable state. In such state, the circuit is unable to settle into a stable high (1) or low (0) voltage state within the required time. Metastability is one of the major design concern for clock domain crossing designs, which we will cover in details later in the book.

1.3.3 Combinational and sequential logic

Combinational logic are logic consist of basic logic such as NAND, NOR, and NOT gate that are “combined” i.e. connected together to produce more complex circuits. Mathematically, a combination logic is a function that map the inputs to outputs. This mapping is deterministic, that is, two sets of identical inputs shall yell two identical outputs.

Sequential logic, on the other hand, outputs values based on both current and past inputs. These past inputs, stored somewhere inside the memory elements, are referred as state of the circuit. Mathematically, it means that the circuit function \(f\) takes two different types of input, \(i\) and \(S\), and produce two kinds of outputs, \(o\) and \(S\prime\). \(S\) is the state of current circuit and \(S\prime\) is the next state after the circuit computes its output.

The states in sequential logic are commonly stored in latches and flip-flops. A latch is a sequential circuit that changes its outputs independently of a clock signal whereas a flip-flop changes its outputs only at times determined by a clock signal. This difference is critical and has implication on how we reason about digital design, as they have different power/timing charastics.

1.3.3.1 Latches

There are many different types of latches. We will discuss only one of them here.

A set/reset latch, or SR latch, works by relying on the the values of the \(S\) and \(R\) signals. It can be made from two NOR gates that have cross-feedback loop, as shown in Figure 1.

The truth table for the SR-Latch is shown in Table 1. Readers are encouraged to work out the details on different \(S\) \(R\) conditions, especially when \(Q\) is metastable.

1.3.3.2 D Flip-Flop

The D-flip-flop is one of the most widely used flip-flop design, as shown in Figure 2. The major difference between D flip-flop and SR latch is that data latched at clock edge. This latching behavior related to clock edges makes the design synchronous. A single D flip-flop can hold 1-bit memory.

There are many variants of D flip-flop that are suitable for various conditions, for instance, classical positive-edge-triggered D flip-flop and master-slave edge-triggered D flip-flop. However, their exact designs are beyond the scope of this book.

Due to the physical constraints on the logic gates, we have two critical timing characteristics regarding synchronous circuit design: setup time and hold time. Setup time refers to the amount of time at the synchronous input before the active clock edge. Hold tim refers to the amount of time at the synchronous input much be stable after the active clock edge, as shown in Figure 3. In other words, the signal has to be stable during both setup and hold time, otherwise there will be a timing violation.

1.4 What will this book cover

SystemVerilog by no means is a complex language and the IEEE 1800-2017 standard spans more than a thousand pages. This book mainly focus on the following aspects of SystemVerilog for digital system design and the EDA tool-chains associated with it:

1. Design technique for digital systems synthesis. The book will first cover comprehensive SystemVerilog language features for synthesis and how they can be used to model hardware. It will focus on vender and technology independent modeling techniques, which can be applied to both ASIC and FPGA design. How to use ASIC/FPGA synthesis tools, however, is beyond the scope of discussion.
2. RTL simulation. This book will gradually transit from simple test bench to object-oriented and reusable test bench design.
3. Software co-verification. This book will cover Verilog Procedural Interface (VPI) and Direct Programming Interface (DPI) in details and how they can be used to offer functional models for verification as well as perform other useful tasks.
4. SystemVerilog Assertions (SVAs). This book will discuss various usages in details and how can SVAs be used in traditional simulation for coverage reports, and serve a foundation for formal verification.
5. Advanced design techniques. This book will briefly cover topics such as clock domain crossing (CDC) and interconnect protocols.

We hope by the end of book you will be confident in writing SystemVerilog for digital system design and verification.